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HICSS
2003
IEEE

Towards Verifying Parametrised Hardware Libraries with Relative Placement Information

9 years 11 months ago
Towards Verifying Parametrised Hardware Libraries with Relative Placement Information
Abstract— This paper presents a framework for verifying compilation tools for parametrised hardware libraries with placement information. Such libraries are captured in Pebble, a simple declarative language based on Structural VHDL, and can contain placement information to guide circuit layout. Relative placement information enables control of circuit layout at a higher level of ion than placement information in the form of explicit coordinates. We provide a functional specification of a procedure for compiling Pebble programs with relative placement information into Pebble programs with explicit placement coordinate information. We present an overview of the steps for verifying this procedure based on pass separation techniques. The compilation procedure can be used in conjunction with partial evaluation to optimise the size and speed of circuits described using relative placement. Our approach has been used for optimising a pattern matcher design, which results in a 33% reduction ...
Steve McKeever, Wayne Luk, Arran Derbyshire
Added 04 Jul 2010
Updated 04 Jul 2010
Type Conference
Year 2003
Where HICSS
Authors Steve McKeever, Wayne Luk, Arran Derbyshire
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