Trace-driven system-level power evaluation of system-on-a-chip peripheral cores

Our earlier work for fast evaluation of power consumption of general cores in a system-on-a-chip described techniques that involved isolating high-level instructions of a core, measuring gate-level power consumption per instruction, and then annotating a system-level simulation model with the obtained data. In this work, we describe a method for speeding up the evaluation further, through the use of instruction traces and trace simulators for every core, not just microprocessor cores. Our method shows noticeable speedups at an acceptable loss of accuracy. We show that reducing trace sizes can speed up the method even further. The speedups allow for more extensive system-level power exploration and hence better optimization. Keywords System-on-a-chip, low power system design, intellectual property, cores, system-level modeling, parameterized architectures.

• Type: Conference
• Year: 2001
• Where: ASPDAC
• Authors: Tony Givargis, Frank Vahid, Jörg Henkel
• Keywords: ASPDAC 2001, Gate-level Power Consumption, Hardware, Power Consumption, System-level Simulation Model