Trace-Level Reuse

Trace-level reuse is based on the observation that some traces (dynamic sequences of instructions) are frequently repeated during the execution of a program, and in many cases, the instructions that make up such traces have the same source operand values. The execution of such traces will obviously produce the same outcome and thus, their execution can be skipped if the processor records the outcome of previous executions. This paper presents an analysis of the performance potential of trace-level reuse and discusses a preliminary realistic implementation. Like instruction-level reuse, trace-level reuse can improve performance by decreasing resource contention and the latency of some instructions. However, we show that tracelevel reuse is more effective than instruction-level reuse because the former can avoid fetching the instructions of reused traces. This has two important benefits: it reduces the fetch bandwidth requirements, and it increases the effective instruction window size ...

• Type: Conference
• Year: 1999
• Where: ICPP
• Authors: Antonio González, Jordi Tubella, Carlos Molina
• Keywords: Distributed And Parallel Computing, ICPP 1999, Instruction-level Reuse, Instructions, Trace-level Reuse