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2000
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Tradeoff Analysis and Architecture Design of a Hybrid Hardware/Software Sorter

10 years 7 months ago
Tradeoff Analysis and Architecture Design of a Hybrid Hardware/Software Sorter
Sorting long sequences of keys is a problem that occurs in many different applications. For embedded systems, a uniprocessor software solution is often not applicable due to the low performance, while realizing multiprocessor sorting methods on parallel computers is much too expensive with respect to power consumption, physical weight, and cost. We investigate cost/performance tradeoffs for hybrid sorting algorithms that use a mixture of sequential merge sort and systolic insertion sort techniques. We propose a scalable architecture for integer sorting that consists of a uniprocessor and an FPGA-based parallel systolic co-processor. Speedups obtained analytically and experimentally and depending on hardware (cost) constraints are determined as a function of time constants of the uniprocessor and the co-processor.
Marcus Bednara, Oliver Beyer, Jürgen Teich, R
Added 30 Jul 2010
Updated 30 Jul 2010
Type Conference
Year 2000
Where ASAP
Authors Marcus Bednara, Oliver Beyer, Jürgen Teich, Rolf Wanka
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