Transient Power Management Through High Level Synthesis

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Transient Power Management Through High Level Synthesis
The use of nanometer technologies is making it increasingly important to consider transient characteristics of a circuit’s power dissipation (e.g., peak power, and power gradient or differential) in addition to its average power consumption. Current transient power analysis and reduction approaches are mostly at the transistor- and logic-levels. We argue that, as was the case with average power minimization, architectural solutions to transient power problems can complement and significantly extend the scope of lower-level techniques. In this work, we present a high-level synthesis approach to transient power management. We demonstrate how high-level synthesis can impact the cycle-by-cycle peak power and peak power differential for the synthesized implementation. Further, we demonstrate that it is necessary to consider transient power metrics judiciously in order to minimize or avoid area and performance overheads. In order to alleviate the limits on parallelism imposed by peak pow...
Vijay Raghunathan, Srivaths Ravi, Anand Raghunatha
Added 17 Mar 2010
Updated 17 Mar 2010
Type Conference
Year 2001
Authors Vijay Raghunathan, Srivaths Ravi, Anand Raghunathan, Ganesh Lakshminarayana
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