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ICCAD
2000
IEEE

Transistor-Level Timing Analysis Using Embedded Simulation

10 years 2 months ago
Transistor-Level Timing Analysis Using Embedded Simulation
A high accuracy system for transistor-level static timing analysis is presented. Accurate static timing verification requires that individual gate and interconnect delays be accurately calculated. At the sub-micron level, calculating gate and interconnect delays using delay models can result in reduced accuracy. Instead, the proposed method calculates delays through numerical integration using an embedded circuit simulator. It takes into account short circuit current and carefully chooses the set of conditions that results in a tight upper bound of the worst case delay for each gate. Similar repeating transistor configurations of gates in the circuit are automatically identified and a novel interpolation based caching scheme quickly computes gate delays from the delays of similar gates. A tight object code level integration with a commercial high speed transistorlevel circuit simulator allows efficient invocation of the simulation.
Pawan Kulshreshtha, Robert Palermo, Mohammad Morta
Added 31 Jul 2010
Updated 31 Jul 2010
Type Conference
Year 2000
Where ICCAD
Authors Pawan Kulshreshtha, Robert Palermo, Mohammad Mortazavi, Cyrus Bamji, Hakan Yalcin
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