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ASPDAC
1995
ACM

Transistor reordering rules for power reduction in CMOS gates

9 years 7 months ago
Transistor reordering rules for power reduction in CMOS gates
— The goal of transistor reordering for a logic gate is to reduce the propagation delay as well as the charging and discharging of internal capacitances to achieve low power consumption. In this paper, based on the input signal probabilities and transition densities, we propose a set of simple transistor reordering rules for both basic and complex CMOS gates to minimize the transition counts at the internal nodes. The most attractive feature of this approach is that not only the power consumption is reduced efficiently, but also the other performances are not degraded. Experimental results show that this technique typically reduces the power by about 10% in average, but in some cases the improvement is even 35%.
Wen-Zen Shen, Jiing-Yuan Lin, Fong-Wen Wang
Added 25 Aug 2010
Updated 25 Aug 2010
Type Conference
Year 1995
Where ASPDAC
Authors Wen-Zen Shen, Jiing-Yuan Lin, Fong-Wen Wang
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