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DAC
1997
ACM

Transistor Sizing Issues and Tool For Multi-Threshold CMOS Technology

10 years 11 days ago
Transistor Sizing Issues and Tool For Multi-Threshold CMOS Technology
Multi-threshold CMOS is an increasingly popular circuit approach that enables high performance and low power operation. However, no methodologies have been developed to size the high Vt sleep transistor in an intelligent manner that trades off area and performance. In fact, many attempts at sizing the sleep transistor without close consideration of input vector patterns or internal structures can lead to large overestimates or large underestimates in sleep transistor sizing. This paper describes some of the issues involved in sizing transistors for MTCMOS and also introduces a variable breakpoint switch level simulator that can rapidly calculate delay in MTCMOS circuits as functions of design variables such as Vdd, Vt, and sleep transistor sizing.
James Kao, Anantha Chandrakasan, Dimitri Antoniadi
Added 06 Aug 2010
Updated 06 Aug 2010
Type Conference
Year 1997
Where DAC
Authors James Kao, Anantha Chandrakasan, Dimitri Antoniadis
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