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ICCD
2007
IEEE

Transparent mode flip-flops for collapsible pipelines

11 years 5 months ago
Transparent mode flip-flops for collapsible pipelines
Prior work has shown that collapsible pipelining techniques have the potential to significantly reduce clocking activity, which can consume up to 70% of the dynamic power in modern high performance microprocessors. Previous collapsible pipeline proposals either rely on single phase clocking (by forcing latches into transparent state) or do not discuss the mechanisms by which stages are merged. In this work two flip-flop designs featuring an additional transparent state suitable for collapsing stages are presented. Transparency is achieved either by decoupling the master and slave clocks to keep both latches transparent, or by using a bypass mux that routes around the flip-flop. Both of these designs are evaluated in the context of transparently gated pipelines, an ad-hoc collapsible pipelining technique. Detailed analysis shows that the decoupled clock flipflop is the most attractive in terms of energy and delay.
Eric L. Hill, Mikko H. Lipasti
Added 16 Aug 2010
Updated 16 Aug 2010
Type Conference
Year 2007
Where ICCD
Authors Eric L. Hill, Mikko H. Lipasti
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