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ICPP
1991
IEEE

Two Techniques to Enhance the Performance of Memory Consistency Models

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Two Techniques to Enhance the Performance of Memory Consistency Models
The memory consistency model supported by a multiprocessor directly affects its performance. Thus, several attempts have been made to relax the consistency models to allow for more buffering and pipelining of memory accesses. Unfortunately, the potential increase in performance afforded by relaxing the consistency model is accompanied by a more complex programming model. This paper introduces two general implementation techniques that provide higher performance for all the models. The first technique involves prefetching values for accesses that are delayed due to consistency model constraints. The second technique employs speculative execution to allow the processor to proceed even though the consistency model requires the memory accesses to be delayed. When combined, the above techniques alleviate the limitations imposed by a consistency model on buffering and pipelining of memory accesses, thus significantly reducing the impact of the memory consistency model on performance.
Kourosh Gharachorloo, Anoop Gupta, John L. Henness
Added 27 Aug 2010
Updated 27 Aug 2010
Type Conference
Year 1991
Where ICPP
Authors Kourosh Gharachorloo, Anoop Gupta, John L. Hennessy
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