Understanding and minimizing ground bounce during mode transition of power gating structures

We introduce and analyze the ground bounce due to power mode transition in power gating structures. To reduce the ground bounce, we propose novel power gating structures in which sleep transistors are turned on in a non-uniform stepwise manner. Our power gating structures reduce the magnitude of peak current and voltage glitches in the power distribution network as well as the minimum time required to stabilize power and ground. Experimental simulation results with PowerSpice fixtured in a package model demonstrate the effectiveness of the proposed power gate switching noise reduction techniques. Categories and Subject Descriptors B.7.1 [Integrated Circuits]: Types and Design Styles— advanced technologies, microprocessor and microcomputers General Terms Reliability Design Keywords clock gating, power gating, wake-up latency, inductive noise, ground bounce, system-on-a-chip (SOC) design.

• Type: Conference
• Year: 2003
• Where: ISLPED
• Authors: Suhwan Kim, Stephen V. Kosonocky, Daniel R. Knebel
• Keywords: Gating, Ground Bounce, ISLPED 2003, Power Gating Structures