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2006
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Upper Bounding Fault Coverage by Structural Analysis and Signal Monitoring

12 years 3 months ago
Upper Bounding Fault Coverage by Structural Analysis and Signal Monitoring
A new algorithm for identifying stuck faults in combinational circuits that cannot be detected by a given input sequence is presented. Other than pre and post-processing steps, certain signal conditions are monitored during logic simulation. These signal conditions are specified by an analysis of dominators and signal reconvergences in the circuit graph. After simulation, a post-processing step identifies faults that cannot be detected by the sequence. For combinational ISCAS benchmarks, the runtime overhead for the algorithm is found to be around 30-40% over that of a logic simulator. Experimental data show a substantial reduction of error in statistical estimates obtained by a stuck-fault coverage estimator when corrected for faults found by this algorithm as guaranteed to be undetected by the given sequence. An effective application of this technique is demonstrated for scan-based test point selection in an industrial scenario where circuit size and vector length prohibit the us...
Vishwani D. Agrawal, Soumitra Bose, Vijay Gangaram
Added 12 Jun 2010
Updated 12 Jun 2010
Type Conference
Year 2006
Where VTS
Authors Vishwani D. Agrawal, Soumitra Bose, Vijay Gangaram
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