Use of Sensitivities and Generalized Substrate Models in Mixed-Signal IC Design

A novel methodology for circuit design and automatic layout generation is proposed for a class of mixed-signal circuits in presence of layout parasitics and substrate induced noise. Accurate and efficient evaluationof the circuit during designis possiblebytaking into account such non-idealities. Techniques are presented to derive and use a set of constraints on substrate noise and on the geometric instances of the layout. Verification is performed using substrate extraction in combination with parasitic estimation techniques. To show the suitability of the approach, a VCO for a PLL has been designed and implemented in a CMOS 1m technology. The circuit has been optimized both at the schematic and at the layout level for power and performance, while its sensitivity to layout parasitics and substrate noise has been minimized.

• Type: Conference
• Year: 1996
• Where: DAC
• Authors: Paolo Miliozzi, Iasson Vassiliou, Edoardo Charbon, Enrico Malavasi, Alberto L. Sangiovanni-Vincentelli
• Keywords: Computer Architecture, DAC 1996, Layout Parasitics, Substrate Induced Noise, Substrate Noise