Sciweavers

Share
CODES
2009
IEEE

Using binary translation in event driven simulation for fast and flexible MPSoC simulation

9 years 2 months ago
Using binary translation in event driven simulation for fast and flexible MPSoC simulation
In this paper, we investigate the use of instruction set simulators (ISS) based on binary translation to accelerate full timed multiprocessor system simulation at transaction level. To have an accurate timing behavior, we had to firstly solve timing issues in processor modeling, secondly define fast and precise cache models, and thirdly solve the synchronization issues due to the different models of computation used in the ISSes and in the rest of the system. We present an integration solution that covers these issues and detail its implementation. We have experimented our proposal using processors models provided by the QEMU framework to replace the existing ISSes and SystemC TLM as simulation environment for the whole platform. This approach proposes a range of solutions trading off simulation speed versus accuracy. The experiments show that even for the most precise configuration, the simulation speedup is still significant. Categories and Subject Descriptors C.0 [Computer Syst...
Marius Gligor, Nicolas Fournel, Frédé
Added 20 May 2010
Updated 20 May 2010
Type Conference
Year 2009
Where CODES
Authors Marius Gligor, Nicolas Fournel, Frédéric Pétrot
Comments (0)
books