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FPL
2005
Springer

Using DSP Blocks For ROM Replacement: A Novel Synthesis Flow

13 years 9 months ago
Using DSP Blocks For ROM Replacement: A Novel Synthesis Flow
This paper describes a method based on polynomial approximation for transferring ROM resources used in FPGA designs to multiplication and addition operations. The technique can be applied to any FPGA architecture containing embedded multiplication, however this paper focuses on using the DSP blocks of Altera Stratix and Stratix II architectures. The transformation is combined with other resource transfers and integrated in a synthesis flow targeting designs implemented on heterogeneous FPGAs. The main advantage of such a system is in handling user constraints on each type of resource: DSP block, LUT and ROM, in addition to timing-related constraints. The flow is based on an extension to the Altera Quartus II synthesis software and Quartus University Interface Program (QUIP) framework. Results are provided for implementations of benchmark algorithms and it is shown through a design-space exploration that the set of achievable designs for the algorithms has been extended by the use of...
Gareth W. Morris, George A. Constantinides, Peter
Added 27 Jun 2010
Updated 27 Jun 2010
Type Conference
Year 2005
Where FPL
Authors Gareth W. Morris, George A. Constantinides, Peter Y. K. Cheung
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