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FDL
2003
IEEE

Using Symbolic Simulation for Bounded Property Checking

13 years 9 months ago
Using Symbolic Simulation for Bounded Property Checking
Assuring correctness of digital designs is one of the major tasks in the system design flow. Formal methods have been proposed to accompany commonly used simulation approaches. In this paper we describe a new technique of property checking using symbolic simulation which can be applied to larger designs. This technique seamlessly integrate formal verification and standard simulation. The proposed method is a formal verification technique which checks symbolically a given LTL specification against the Hardware Design. Our experimental results show a run time gain over standard symbolic model checking and SAT-based bounded model checking for certain classes of circuits and properties.
Jürgen Ruf, Prakash Mohan Peranandam, Thomas
Added 04 Jul 2010
Updated 04 Jul 2010
Type Conference
Year 2003
Where FDL
Authors Jürgen Ruf, Prakash Mohan Peranandam, Thomas Kropf, Wolfgang Rosenstiel
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