Variability-Aware Bulk-MOS Device Design

8 years 11 months ago
Variability-Aware Bulk-MOS Device Design
As CMOS technology is scaled down toward the nanoscale regime, drastically growing leakage currents and variations in device characteristics are becoming two important design challenges. Traditionally, the device-design methodology is based on finding the device parameters which minimize the leakage current while providing a minimum saturation current for the transistor. This methodology may change when variations are accounted for design. In this paper, a novel device optimization methodology is presented that incorporates variability awareness into the device-design flow such that the designed device satisfies desired bounds on total leakage, saturation current, and intrinsic delay under parameter variabilities. The technique locates the maximum-yield rectangular cube in the 5-D feasible space composed of oxide-thickness, gate-length, and channel-doping profile parameters. The center of this cube is considered as the maximum-yield design point with the highest immunity against variat...
Javid Jaffari, Mohab Anis
Added 15 Dec 2010
Updated 15 Dec 2010
Type Journal
Year 2008
Where TCAD
Authors Javid Jaffari, Mohab Anis
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