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2005
IEEE

Variable Resizing for Area Improvement in Behavioral Synthesis

10 years 11 months ago
Variable Resizing for Area Improvement in Behavioral Synthesis
High level synthesis tools transform an algorithmic description to a register transfer language (RTL) description of the hardware. The algorithm behavior is typically described in languages like C, C++ or their variants. The generated RTL is described in a hardware specification language like VHDL or Verilog. The size of the variables specified in the algorithm has a significant impact on the area of the generated hardware. The language accepted by the High Level Synthesis tools typically allow the size or bit width of a variable to be specified explicitly. This paper describes a method to automatically determine the minimum bit width of the variables from a performance profile. This would be effective to reduce the combinatorial and the noncombinatorial area of the generated hardware.
R. Gopalakrishnan, Rajat Moona
Added 01 Dec 2009
Updated 01 Dec 2009
Type Conference
Year 2005
Where VLSID
Authors R. Gopalakrishnan, Rajat Moona
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