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Variation-Aware Application Scheduling and Power Management for Chip Multiprocessors

9 years 5 months ago
Variation-Aware Application Scheduling and Power Management for Chip Multiprocessors
Within-die process variation causes individual cores in a Chip Multiprocessor (CMP) to differ substantially in both static power consumed and maximum frequency supported. In this environment, ignoring variation effects when scheduling applications or when managing power with Dynamic Voltage and Frequency Scaling (DVFS) is suboptimal. This paper proposes variation-aware algorithms for application scheduling and power management. One such power management algorithm, called LinOpt, uses linear programming to find the best voltage and frequency levels for each of the cores in the CMP — maximizing throughput at a given power budget. In a 20core CMP, the combination of variation-aware application scheduling and LinOpt increases the average throughput by 12–17% and reduces the average ED2 by 30–38% — all relative to using variation-aware scheduling together with a simple extension to Intel’s Foxton power management algorithm.
Radu Teodorescu, Josep Torrellas
Added 31 May 2010
Updated 31 May 2010
Type Conference
Year 2008
Where ISCA
Authors Radu Teodorescu, Josep Torrellas
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