Variation-Aware System-Level Power Analysis

Abstract-- The operational characteristics of integrated circuits based on nanoscale semiconductor technology are expected to be increasingly affected by variations in the manufacturing process and the operating environment. Researchers have proposed various design techniques to address such variations at the mask, circuit, and logic levels. However, as the impact of such variations increases, their effects will need to be considered earlier in the design cycle. In this paper, we address the problem of how to incorporate the effects of variations into system-level power analysis tools. We consider both manufacturing induced (die-to-die and withindie) variations in device characteristics, as well as operation induced dynamic variations in on-chip temperature. To motivate our work, we first analyze the impact of variations on the power consumption of an example SoC design. We show how simple extensions of current approaches to system-level power estimation (based on design spreadsheets, ...

• Type: Journal
• Year: 2010
• Where: TVLSI
• Authors: Saumya Chandra, Kanishka Lahiri, Anand Raghunathan, Sujit Dey
• Keywords: Artificial Intelligence, Power Consumption, SoC Power, System-level Power Estimation, TVLSI 2010