Verification Methodologies in a TLM-to-RTL Design Flow

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Verification Methodologies in a TLM-to-RTL Design Flow
SoC based system developments commonly employ ESL design ogies and utilize multiple levels of abstract models to provide feasibility study models for architects and development platforms for software engineers. Such models are evolving to stract models as the development moves forward. The correctness of these models coupled with the ability of having a temporal debug environment to identify and fix model issues is critical for both hardware and software development efforts that make use of such models. This paper presents the mechanism to t temporal assertions at models in various abstract levels e the assertions on models at different abstract level. Categories and Subject Descriptors J.6 [COMPUTER-AIDED ENGINEERING]: Computer-aided design (CAD) General Terms Measurement, Performance, Design, Reliability, Standardization, Languages, Verification. Keywords SystemC, Assertion, Verification, TLM, PV, PVT.
Atsushi Kasuya, Tesh Tesfaye
Added 14 Aug 2010
Updated 14 Aug 2010
Type Conference
Year 2007
Where DAC
Authors Atsushi Kasuya, Tesh Tesfaye
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