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EURODAC
1995
IEEE

VHDL-based communication and synchronization synthesis

9 years 10 months ago
VHDL-based communication and synchronization synthesis
This paper describes an approach for VHDL-based communication and synchronization synthesis. This design step transforms a system level VHDL description into an RT-level description. The idea is, not to synthesize system level implementations of communication and synchronization mechanisms but to perform hesis step as a mapping step of an abstract communication or synchronization mechanism to one of a set of RT-level implementations. The major sub-problem, which needed to be solved for the synthesis algorithm was the topology dependent mapping of implementations.
Wolfgang Ecker, Manfred Huber
Added 26 Aug 2010
Updated 26 Aug 2010
Type Conference
Year 1995
Where EURODAC
Authors Wolfgang Ecker, Manfred Huber
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