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Virtual Simple Architecture (VISA): Exceeding the Complexity Limit in Safe Real-Time Systems

9 years 5 months ago
Virtual Simple Architecture (VISA): Exceeding the Complexity Limit in Safe Real-Time Systems
Meeting deadlines is a key requirement in safe realtime systems. Worst-case execution times (WCET) of tasks are needed for safe planning. Contemporary worst-case timing analysis tools can safely and tightly bound execution time on in-order single-issue pipelines with caches and static branch prediction. However, this simple pipeline appears to be a complexity limit, due to the need for analyzability. This excludes a whole class of high-performance processors from many embedded systems. We reconcile the complexity/safety trade-off by decoupling worst-case timing analysis from the processor implementation, through a virtual simple architecture (VISA). A VISA is the timing speciļ¬cation of a hypothetical simple pipeline and is the basis for worst-case timing analysis. However, the underlying microarchitecture can be arbitrarily complex. A task is divided into multiple sub-tasks which provide a means to gauge progress on the complex pipeline. Each sub-task is assigned an interim deadline...
Aravindh Anantaraman, Kiran Seth, Kaustubh Patil,
Added 04 Jul 2010
Updated 04 Jul 2010
Type Conference
Year 2003
Where ISCA
Authors Aravindh Anantaraman, Kiran Seth, Kaustubh Patil, Eric Rotenberg, Frank Mueller
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