Sciweavers

Share
ISCAS
2005
IEEE

VLSI architecture based on packet data transfer scheme and its application

9 years 1 months ago
VLSI architecture based on packet data transfer scheme and its application
Abstract— Packet data transfer scheme is introduced for intrachip data transfer to solve an interconnection problem. Double transmission lines are provided as a platform of the micronetwork. A protocol suitable for intra-chip data transfer is proposed to make a router as simple as possible. An application to a parallel VLSI processor is also discussed. In comparison with a multi-bus architecture the parallelism can be greatly increased under the same chip size because of the compactness of the micronetwork.
Yuya Homma, Michitaka Kameyama, Yoshichika Fujioka
Added 25 Jun 2010
Updated 25 Jun 2010
Type Conference
Year 2005
Where ISCAS
Authors Yuya Homma, Michitaka Kameyama, Yoshichika Fujioka, Nobuhiro Tomabechi
Comments (0)
books