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ASPDAC
2005
ACM

VLSI on-chip power/ground network optimization considering decap leakage currents

10 years 3 months ago
VLSI on-chip power/ground network optimization considering decap leakage currents
- In today’s power/ground(P/G) network design, on-chip decoupling capacitors(decaps) are usually made of MOS transistors with source and drain connected together. The gate leakage current becomes worse as the gate oxide layer thickness continues to shrink below 20Å. As a result, decaps will become leaky due to the gate leakage from CMOS devices. In this paper, we take a first look at the leaky decaps in P/G network optimization. We propose a leakage current model for practical decaps and also present a new two-stage leakage-current-aware approach to efficiently optimize P/G networks in a more area efficient way.
Jingjing Fu, Zuying Luo, Xianlong Hong, Yici Cai,
Added 26 Jun 2010
Updated 26 Jun 2010
Type Conference
Year 2005
Where ASPDAC
Authors Jingjing Fu, Zuying Luo, Xianlong Hong, Yici Cai, Sheldon X.-D. Tan, Zhu Pan
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