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2007
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VLSI Decoder Architecture for High Throughput, Variable Block-size and Multi-rate LDPC Codes

9 years 5 months ago
VLSI Decoder Architecture for High Throughput, Variable Block-size and Multi-rate LDPC Codes
Abstract— A low-density parity-check (LDPC) decoder architecture that supports variable block sizes and multiple code rates is presented. The proposed architecture is based on the structured quasi-cyclic (QC-LDPC) codes whose performance compares favorably with that of randomly constructed LDPC codes for short to moderate block sizes. The main contribution of this work is to address the variable block-size and multirate decoder hardware complexity that stems from the irregular LDPC codes. The overall decoder, which was synthesized, placed and routed on TSMC 0.13-micron CMOS technology with a core area of 4.5 square millimeters, supports variable code lengths from 360 to 4200 bits and multiple code rates between 1/4 and 9/10. The average throughput can achieve 1 Gbps at 2.2 dB SNR.
Yang Sun, Marjan Karkooti, Joseph R. Cavallaro
Added 04 Jun 2010
Updated 04 Jun 2010
Type Conference
Year 2007
Where ISCAS
Authors Yang Sun, Marjan Karkooti, Joseph R. Cavallaro
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