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DAC
2004
ACM

Worst-case circuit delay taking into account power supply variations

10 years 11 months ago
Worst-case circuit delay taking into account power supply variations
Current Static Timing Analysis (STA) techniques allow one to verify the timing of a circuit at different process corners which only consider cases where all the supplies are low or high. This analysis may not give the true maximum delay of a circuit because it neglects the possible mismatch between drivers and loads. We propose a new approach for timing analysis in which we first identify the critical path(s) of a circuit using a power-supply-aware timing model. Given these critical paths, we then take into account how the power nodes of the gates on the critical path are connected to the power grid, and re-analyze for the worst-case time delay. This re-analysis is posed as an optimization problem where lete operation of the entire circuit is abstracted in terms of current constraints. We present our technique and report on the implementation results using benchmark circuits tied to a number of test-case power grids. Categories and Subject Descriptors B.7 [Integrated Circuits]: Design...
Dionysios Kouroussis, Rubil Ahmadi, Farid N. Najm
Added 13 Nov 2009
Updated 13 Nov 2009
Type Conference
Year 2004
Where DAC
Authors Dionysios Kouroussis, Rubil Ahmadi, Farid N. Najm
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