Yield enhancement of asynchronous logic circuits through 3-dimensional integration technology

This paper presents a systematic design methodology for yield enhancement of asynchronous logic circuits using 3-D (3-Dimensional) integration technology. In this design, the target asynchronous circuits on one planar device layer, are fabricated with aggressive technology and built on fault tolerant graph models with extra spare resources. In the presence of hard errors, these circuits can be reconfigured by autonomous reconfiguration logic on another planar device layer fabricated with conservative technology. The yield analysis shows that this method can result in 20–30% overall yield enhancement. This design method can be conveniently applied to clocked designs without significant changes. Categories and Subject Descriptors: B.6.2 [Logic Design]: Reliability and Testing – Redundant Design General Terms: Design

• Type: Conference
• Year: 2006
• Where: GLVLSI
• Authors: Song Peng, Rajit Manohar
• Keywords: Asynchronous Logic Circuits, GLVLSI 2006, Planar Device Layer, VLSI, Yield Enhancement