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DFT
1999
IEEE

Yield Estimation of VLSI Circuits with Downscaled Layouts

13 years 8 months ago
Yield Estimation of VLSI Circuits with Downscaled Layouts
This paper describes the yield estimation approach to layout scaling of submicron VLSI circuits. The presented method makes it feasible to find scaling factor of the IC design which is optimal from the manufacturing yield point of view. It also allows to reduce time-consuming extraction of the critical area functions. Examples of yield calculations using the proposed method are presented as well.
Witold A. Pleskacz
Added 03 Aug 2010
Updated 03 Aug 2010
Type Conference
Year 1999
Where DFT
Authors Witold A. Pleskacz
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