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FPL
2005
Springer

Yield modelling and Yield Enhancement for FPGAs using Fault Tolerance Schemes

13 years 9 months ago
Yield modelling and Yield Enhancement for FPGAs using Fault Tolerance Schemes
This paper presents a revised model for the yield analysis of FPGA interconnect layers. Based on proven yield models, this work improves the predictions and assumptions of previously reported analysis. The model is then applied to three well known yield improvement schemes to quantify the enhancement offered by these schemes.
Nicola Campregher, Peter Y. K. Cheung, George A. C
Added 27 Jun 2010
Updated 27 Jun 2010
Type Conference
Year 2005
Where FPL
Authors Nicola Campregher, Peter Y. K. Cheung, George A. Constantinides, Milan Vasilko
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