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ISCA
2011
IEEE
155views Hardware» more  ISCA 2011»
9 months 10 days ago
CPPC: correctable parity protected cache
Due to shrinking feature sizes processors are becoming more vulnerable to soft errors. Write-back caches are particularly vulnerable since they hold dirty data that do not exist i...
Mehrtash Manoochehri, Murali Annavaram, Michel Dub...
ISCA
2011
IEEE
114views Hardware» more  ISCA 2011»
9 months 10 days ago
Dark silicon and the end of multicore scaling
Since 2005, processor designers have increased core counts to exploit Moore’s Law scaling, rather than focusing on single-core performance. The failure of Dennard scaling, to wh...
Hadi Esmaeilzadeh, Emily R. Blem, Renée St....
MTA
2011
96views Hardware» more  MTA 2011»
1 years 14 days ago
SCface - surveillance cameras face database
In this paper we describe a database of static images of human faces. Images were taken in uncontrolled indoor environment using five video surveillance cameras of various qualitie...
Mislav Grgic, Kresimir Delac, Sonja Grgic
ISCA
2011
IEEE
94views Hardware» more  ISCA 2011»
9 months 10 days ago
Architecting on-chip interconnects for stacked 3D STT-RAM caches in CMPs
Emerging memory technologies such as STT-RAM, PCRAM, and resistive RAM are being explored as potential replacements to existing on-chip caches or main memories for future multi-co...
Asit K. Mishra, Xiangyu Dong, Guangyu Sun, Yuan Xi...
MICRO
2011
IEEE
94views Hardware» more  MICRO 2011»
1 years 14 days ago
Thread Cluster Memory Scheduling
In a modern chip-multiprocessor system, memory is a shared resource among multiple concurrently executing threads. The memory scheduling algorithm should resolve memory contention...
Yoongu Kim, Michael Papamichael, Onur Mutlu, Mor H...
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