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» : The Design and Analysis of an Algorithm Portfolio for SAT
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VLSID
2009
IEEE
150views VLSI» more  VLSID 2009»
14 years 5 months ago
TIGUAN: Thread-Parallel Integrated Test Pattern Generator Utilizing Satisfiability ANalysis
We present the automatic test pattern generator TIGUAN based on a thread-parallel SAT solver. Due to a tight integration of the SAT engine into the ATPG algorithm and a carefully ...
Alejandro Czutro, Ilia Polian, Matthew D. T. Lewis...
DAC
2003
ACM
14 years 5 months ago
Learning from BDDs in SAT-based bounded model checking
Bounded Model Checking (BMC) based on Boolean Satisfiability (SAT) procedures has recently gained popularity as an alternative to BDD-based model checking techniques for finding b...
Aarti Gupta, Malay K. Ganai, Chao Wang, Zijiang Ya...
CAV
2009
Springer
212views Hardware» more  CAV 2009»
14 years 5 months ago
Beaver: Engineering an Efficient SMT Solver for Bit-Vector Arithmetic
We present the key ideas in the design and implementation of Beaver, an SMT solver for quantifier-free finite-precision bit-vector logic (QF BV). Beaver uses an eager approach, enc...
Susmit Jha, Rhishikesh Limaye, Sanjit A. Seshia
ICPADS
2007
IEEE
13 years 11 months ago
A scheduling algorithm for revenue maximisation for cluster-based Internet services
This paper proposes a new priority scheduling algorithm to maximise site revenue of session-based multi-tier Internet services in a multicluster environment. This research is part...
James Wen Jun Xue, Ligang He, Stephen A. Jarvis
ESA
2006
Springer
113views Algorithms» more  ESA 2006»
13 years 8 months ago
An LP-Designed Algorithm for Constraint Satisfaction
The class Max (r, 2)-CSP consists of constraint satisfaction problems with at most two r-valued variables per clause. For instances with n variables and m binary clauses, we presen...
Alexander D. Scott, Gregory B. Sorkin