3 search results - page 1 / 1 » 3-Valued Circuit SAT for STE with Automatic Refinement |
ATVA
2007
Springer
13 years 8 months ago
2007
Springer
Abstract. Symbolic Trajectory Evaluation (STE) is a powerful technique for hardware model checking. It is based on a 3-valued symbolic simulation, using 0,1 and X n"), where t...
ACSD
2007
IEEE
13 years 8 months ago
2007
IEEE
Synthesis of asynchronous circuits from Signal Transition Graphs (STGs) involves resolution of state encoding conflicts by means of refining the STG specification. In this paper, ...
ASPDAC
2007
ACM
13 years 8 months ago
2007
ACM
ound in BMC by Combining Constant Propagation and Abstraction Roy Armoni, Limor Fix1 , Ranan Fraer1 , Tamir Heyman1,3 , Moshe Vardi2 , Yakir Vizel1 , Yael Zbar1 1 Logic and Validat...