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    IEICET
    2007
    53views more  IEICET 2007»
    A 1.25-Gb/s Burst-Mode Half-Rate Clock and Data Recovery Circuit Using Realigned Oscillation
    13 years 4 months ago
    A 1.25-Gb/s Burst-Mode Half-Rate Clock and Data Recovery Circuit Using Realigned Oscillation
    Download  www.ee.nchu.edu.tw
    Ching-Yuan Yang, Jung-Mao Lin
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    DAC
    2001
    ACM
    148views Computer Architecture» more  DAC 2001»
    Design of Half-Rate Clock and Data Recovery Circuits for Optical Communication Systems
    14 years 5 months ago
    Design of Half-Rate Clock and Data Recovery Circuits for Optical Communication Systems
    Download  www.ee.ucla.edu
    This paper describes the design of two half-rate clock and data recovery circuits for optical receivers. Targeting the data rate of 10-Gb/s, the rst implementation incorporates a ...
    Jafar Savoj, Behzad Razavi
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