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ISCA
2000
IEEE
81views Hardware» more  ISCA 2000»
13 years 9 months ago
Clock rate versus IPC: the end of the road for conventional microarchitectures
The doubling of microprocessor performance every three years has been the result of two factors: more transistors per chip and superlinear scaling of the processor clock with tech...
Vikas Agarwal, M. S. Hrishikesh, Stephen W. Keckle...
EUROPAR
2001
Springer
13 years 9 months ago
Execution Latency Reduction via Variable Latency Pipeline and Instruction Reuse
Operand bypass logic might be one of the critical structures for future microprocessors to achieve high clock speed. The delay of the logic imposes the execution time budget to be ...
Toshinori Sato, Itsujiro Arita
ICC
2007
IEEE
239views Communications» more  ICC 2007»
13 years 11 months ago
Measuring WCDMA and HSDPA Delay Characteristics with QoSMeT
—Quality of Service (QoS) is becoming increasingly important with the rise of multimedia applications (e.g., voice over IP (VoIP), video conferencing, online gaming, and Internet...
Jarmo Prokkola, Mikko Hanski, Marko Jurvansuu, Mil...
ICCAD
1999
IEEE
97views Hardware» more  ICCAD 1999»
13 years 9 months ago
A methodology for correct-by-construction latency insensitive design
In Deep Sub-Micron (DSM) designs, performance will depend critically on the latency of long wires. We propose a new synthesis methodology for synchronous systems that makes the de...
Luca P. Carloni, Kenneth L. McMillan, Alexander Sa...
HPCA
2003
IEEE
14 years 5 months ago
Control Techniques to Eliminate Voltage Emergencies in High Performance Processors
Increasing focus on power dissipation issues in current microprocessors has led to a host of proposals for clock gating and other power-saving techniques. While generally effectiv...
Russ Joseph, David Brooks, Margaret Martonosi