3 search results - page 1 / 1 » A Bridging Fault Model Where Undetectable Faults Imply Logic... |
DATE
2008
IEEE
13 years 11 months ago
2008
IEEE
We define a robust fault model as a model where the existence of an undetectable fault implies the existence of logic redundancy, or more generally, a suboptimality in the synthe...
MTDT
2002
IEEE
13 years 10 months ago
2002
IEEE
The amount of memory being embedded on chip is growing rapidly. This strongly implies that memory Built-in-self-test (BIST) logic assumes utmost importance amongst all on chip sel...
EDCC
2008
Springer
13 years 7 months ago
2008
Springer
The ongoing technological advances in the semiconductor industry make Multi-Processor System-on-a-Chips (MPSoCs) more attractive, because uniprocessor solutions do not scale satis...