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ICCD
2006
IEEE
189views Hardware» more  ICCD 2006»
14 years 1 months ago
A Capacity Co-allocation Configurable Cache for Low Power Embedded Systems
— Traditional level-one instruction caches and data caches for embedded systems typically have the same capacities. Configurable caches either shut down a part of the cache to su...
Chuanjun Zhang
DAC
1999
ACM
14 years 5 months ago
Memory Exploration for Low Power, Embedded Systems
In embedded system design, the designer has to choose an onchip memory configuration that is suitable for a specific application. To aid in this design choice, we present a memory...
Wen-Tsong Shiue, Chaitali Chakrabarti
CODES
2005
IEEE
13 years 6 months ago
An efficient direct mapped instruction cache for application-specific embedded systems
Caches may consume half of a microprocessor’s total power and cache misses incur accessing off-chip memory, which is both time consuming and energy costly. Therefore, minimizing...
Chuanjun Zhang
ISCAS
2002
IEEE
118views Hardware» more  ISCAS 2002»
13 years 9 months ago
A power-configurable bus for embedded systems
Pre-designed configurable platforms, possessing microprocessors, memories, and numerous peripherals on a single chip, are increasing in popularity in embedded system design. Platf...
Chuanjun Zhang, Frank Vahid
ISVLSI
2008
IEEE
158views VLSI» more  ISVLSI 2008»
13 years 11 months ago
Improving Energy Efficiency of Configurable Caches via Temperature-Aware Configuration Selection
Active power used to be the primary contributor to total power dissipation of CMOS designs, but with the technology scaling, the share of leakage in total power consumption of dig...
Hamid Noori, Maziar Goudarzi, Koji Inoue, Kazuaki ...