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» A Certifying Code Generation Phase
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IEEEPACT
2002
IEEE
13 years 9 months ago
A Framework for Parallelizing Load/Stores on Embedded Processors
Many modern embedded processors (esp. DSPs) support partitioned memory banks (also called X-Y memory or dual bank memory) along with parallel load/store instructions to achieve co...
Xiaotong Zhuang, Santosh Pande, John S. Greenland ...
ISSTA
2009
ACM
13 years 11 months ago
HAMPI: a solver for string constraints
Many automatic testing, analysis, and verification techniques for programs can be effectively reduced to a constraint-generation phase followed by a constraint-solving phase. Th...
Adam Kiezun, Vijay Ganesh, Philip J. Guo, Pieter H...
ECCV
2002
Springer
14 years 6 months ago
Tracking and Rendering Using Dynamic Textures on Geometric Structure from Motion
Estimating geometric structure from uncalibrated images accurately enough for high quality rendering is difficult. We present a method where only coarse geometric structure is trac...
Dana Cobzas, Martin Jägersand
PPOPP
2009
ACM
14 years 5 months ago
Transactional memory with strong atomicity using off-the-shelf memory protection hardware
This paper introduces a new way to provide strong atomicity in an implementation of transactional memory. Strong atomicity lets us offer clear semantics to programs, even if they ...
Martín Abadi, Tim Harris, Mojtaba Mehrara
PLDI
2009
ACM
13 years 11 months ago
Parallelizing sequential applications on commodity hardware using a low-cost software transactional memory
Multicore designs have emerged as the mainstream design paradigm for the microprocessor industry. Unfortunately, providing multiple cores does not directly translate into performa...
Mojtaba Mehrara, Jeff Hao, Po-Chun Hsu, Scott A. M...