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» A Compact Transactional Memory Multiprocessor System on FPGA
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ARITH
2009
IEEE
14 years 4 days ago
A Dual-Purpose Real/Complex Logarithmic Number System ALU
—The real Logarithmic Number System (LNS) allows fast and inexpensive multiplication and division but more expensive addition and subtraction as precision increases. Recent advan...
Mark G. Arnold, Sylvain Collange
HPCA
2000
IEEE
13 years 9 months ago
Impact of Chip-Level Integration on Performance of OLTP Workloads
With increasing chip densities, future microprocessor designs have the opportunity to integrate many of the traditional systemlevel modules onto the same chip as the processor. So...
Luiz André Barroso, Kourosh Gharachorloo, A...
INFOCOM
2006
IEEE
13 years 11 months ago
Reverse Hashing for High-Speed Network Monitoring: Algorithms, Evaluation, and Applications
— A key function for network traffic monitoring and analysis is the ability to perform aggregate queries over multiple data streams. Change detection is an important primitive w...
Robert T. Schweller, Zhichun Li, Yan Chen, Yan Gao...
VEE
2005
ACM
218views Virtualization» more  VEE 2005»
13 years 11 months ago
The pauseless GC algorithm
Modern transactional response-time sensitive applications have run into practical limits on the size of garbage collected heaps. The heap can only grow until GC pauses exceed the ...
Cliff Click, Gil Tene, Michael Wolf
ISCA
2000
IEEE
103views Hardware» more  ISCA 2000»
13 years 9 months ago
Piranha: a scalable architecture based on single-chip multiprocessing
The microprocessor industry is currently struggling with higher development costs and longer design times that arise from exceedingly complex processors that are pushing the limit...
Luiz André Barroso, Kourosh Gharachorloo, R...