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» A Comparison of Linear Processor Arrays for Image Processing
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PARELEC
2006
IEEE
13 years 11 months ago
Hierarchical Partitioning for Piecewise Linear Algorithms
processor arrays can be used as accelerators for a plenty of data flow-dominant applications. The explosive growth in research and development of massively parallel processor arr...
Hritam Dutta, Frank Hannig, Jürgen Teich
ICPPW
2006
IEEE
13 years 11 months ago
Retargeting Image-Processing Algorithms to Varying Processor Grain Sizes
Embedded computing architectures can be designed to meet a variety of application specific requirements. However, optimized hardware can require compiler support to realize the po...
Sam Sander, Linda M. Wills
ASAP
2006
IEEE
169views Hardware» more  ASAP 2006»
13 years 12 months ago
A Design Methodology for Hardware Acceleration of Adaptive Filter Algorithms in Image Processing
Massively parallel processor array architectures can be used as hardware accelerators for a plenty of dataflow dominant applications. Bilateral filtering is an example of a stat...
Hritam Dutta, Frank Hannig, Jürgen Teich, Ben...
IPPS
1996
IEEE
13 years 10 months ago
Implementation of a SliM Array Processor
This paper presents the design and implementation of a Sliding Memory Plane (SliM) Array Processor, a mesh-connected SIMD architecture. To build the array processor, we developed ...
Hyun M. Chang, Myung Hoon Sunwoo, Tai-Hoon Cho
IPPS
1999
IEEE
13 years 10 months ago
Real-Time Image Processing on a Focal Plane SIMD Array
Real-time image processing applications have tremendous computational workloads and I/O throughput requirements. Operation in mobile, portable devices poses stringent resource limi...
Antonio Gentile, José Cruz-Rivera, D. Scott...