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» A Compatible Approach to Temporal Description Logics
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MEMOCODE
2003
IEEE
13 years 10 months ago
LOTOS Code Generation for Model Checking of STBus Based SoC: the STBus interconnect
In the design process of SoC (System on Chip), validation is one of the most critical and costly activity. The main problem for industrial companies like STMicroelectronics, stand...
Pierre Wodey, Geoffrey Camarroque, Fabrice Baray, ...
SRDS
1999
IEEE
13 years 9 months ago
Formal Hazard Analysis of Hybrid Systems in cTLA
Hybrid systems like computer-controlled chemical plants are typical safety critical distributed systems. In present practice, the safety of hybrid systems is guaranteed by hazard ...
Peter Herrmann, Heiko Krumm