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VLSID
2006
IEEE
150views VLSI» more  VLSID 2006»
14 years 4 months ago
A Comprehensive SoC Design Methodology for Nanometer Design Challenges
SoC design methodologies are under constant revision due to adoption of fast shrinking process technologies at nanometer levels. Nanometer process geometries exhibit new complex d...
R. Raghavendra Kumar, Ricky Bedi, Ramadas Rajagopa...
DAC
2002
ACM
14 years 5 months ago
Embedded software-based self-testing for SoC design
At-speed testing of high-speed circuits is becoming increasingly difficult with external testers due to the growing gap between design and tester performance, growing cost of high...
Angela Krstic, Wei-Cheng Lai, Kwang-Ting Cheng, Li...
COMPUTER
2002
129views more  COMPUTER 2002»
13 years 4 months ago
Networks on Chips: A New SoC Paradigm
of abstraction and coarse granularity and distributed communication control. Focusing on using probabilistic metrics such as average values or variance to quantify design objective...
Luca Benini, Giovanni De Micheli
DAC
2006
ACM
14 years 5 months ago
Prototyping a fault-tolerant multiprocessor SoC with run-time fault recovery
Modern integrated circuits (ICs) are becoming increasingly complex. The complexity makes it difficult to design, manufacture and integrate these high-performance ICs. The advent o...
Xinping Zhu, Wei Qin
ICCAD
2006
IEEE
208views Hardware» more  ICCAD 2006»
14 years 1 months ago
Automation in mixed-signal design: challenges and solutions in the wake of the nano era
The use of CMOS nanometer technologies at 65 nm and below will pose serious challenges on the design of mixed-signal integrated systems in the very near future. Rising design comp...
Trent McConaghy, Georges G. E. Gielen