6 search results - page 1 / 2 » A Design Flow and Evaluation Framework for DPA-Resistant Ins... |
CHES
2009
Springer
13 years 11 months ago
2009
Springer
Power-based side channel attacks are a significant security risk, especially for embedded applications. To improve the security of such devices, protected logic styles have been p...
VLSID
2006
IEEE
14 years 5 months ago
2006
IEEE
Performance of applications can be boosted by executing application-specific Instruction Set Extensions (ISEs) on a specialized hardware coupled with a processor core. Many commer...
MOBILIGHT
2010
13 years 2 months ago
2010
Abstract. This paper describes a framework for the design space exploration of resource-efficient software-defined radio architectures. This design space exploration is based on a ...
PATMOS
2004
Springer
13 years 10 months ago
2004
Springer
Abstract. An extensible and configurable processor is a programmable platform offering the possibility to customize the instruction set and/or underlying microarchitecture. Efficie...
ARC
2006
Springer
13 years 8 months ago
2006
Springer
We introduce a new paradigm in the computer architecture referred to as Polymorphic Instruction Set Computers (PISC). This new paradigm, in difference to RISC/CISC, introduces hard...