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ICS
2007
Tsinghua U.
13 years 11 months ago
An L2-miss-driven early register deallocation for SMT processors
The register file is one of the most critical datapath components limiting the number of threads that can be supported on a Simultaneous Multithreading (SMT) processor. To allow t...
Joseph J. Sharkey, Dmitry V. Ponomarev
IEEEPACT
2007
IEEE
13 years 11 months ago
CacheScouts: Fine-Grain Monitoring of Shared Caches in CMP Platforms
As multi-core architectures flourish in the marketplace, multi-application workload scenarios (such as server consolidation) are growing rapidly. When running multiple application...
Li Zhao, Ravi R. Iyer, Ramesh Illikkal, Jaideep Mo...
CCR
2008
106views more  CCR 2008»
13 years 5 months ago
Message-efficient dissemination for loop-free centralized routing
With steady improvement in the reliability and performance of communication devices, routing instabilities now contribute to many of the remaining service degradations and interru...
Haldane Peterson, Soumya Sen, Jaideep Chandrasheka...
MSWIM
2005
ACM
13 years 10 months ago
Adaptive transmission opportunity with admission control for IEEE 802.11e networks
The increase of IEEE 802.11’s bandwidth led to a deployment of many multimedia applications over wireless networks. Nevertheless, these applications impose stringent constraints...
Adlen Ksentini, Abdelhak Guéroui, Mohamed N...
IPPS
2010
IEEE
13 years 2 months ago
Adapting cache partitioning algorithms to pseudo-LRU replacement policies
Abstract-- Recent studies have shown that cache partitioning is an efficient technique to improve throughput, fairness and Quality of Service (QoS) in CMP processors. The cache par...
Kamil Kedzierski, Miquel Moretó, Francisco ...