13 search results - page 1 / 3 » A Distributed FIFO Scheme for System on Chip Inter-Component... |
CSREAESA
2004
13 years 5 months ago
2004
Interconnect delays are increasingly becoming the dominant source of performance degradation in the nano-meter regime, largely because the wires do not scale as fast as the device...
ISCAS
2005
IEEE
13 years 10 months ago
2005
IEEE
— Interconnect delays are increasingly becoming the dominant source of performance degradation in the nano-meter regime, largely because of disturbances that result from parasiti...
ISLPED
2005
ACM
13 years 10 months ago
2005
ACM
Due to difficulties in distributing a single global clock signal over increasingly large chip areas, a globally asynchronous, locally synchronous design is considered a promising ...
ICCD
1996
IEEE
13 years 8 months ago
1996
IEEE
This paper describes a novel communication scheme, which is guaranteed to be free of synchronization failures, amongst multiple synchronous modules operating independently. In thi...
ETS
2010
IEEE
13 years 5 months ago
2010
IEEE
Post-silicon validation and debug, or ensuring that software executes correctly on the silicon of a multi-processor system-on-chip (MPSOC) is complicated, as it involves checking g...