4 search results - page 1 / 1 » A Double Precision Floating Point Multiplier Suitably Design... |
CDES
2006
13 years 6 months ago
2006
In this paper, a double precision IEEE 754 floating-point multiplier with high speed and low power is presented. The bottleneck of any double precision floatingpoint multiplier des...
DSD
2003
IEEE
13 years 10 months ago
2003
IEEE
Double precision floating-point arithmetic is inadequate for many scientific computations. This paper presents the design of a quadruple precision floating-point multiplier tha...
ARITH
2007
IEEE
13 years 11 months ago
2007
IEEE
The floating-point multiply-add fused (MAF) unit sets a new trend in the processor design to speed up floatingpoint performance in scientific and multimedia applications. This ...
ERSA
2004
13 years 6 months ago
2004
Abstract-- Technological advances have made FPGAs an attractive platform for the acceleration of complex scientific applications. These applications demand high performance and hig...