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» A Dynamically Adaptable Hardware Transactional Memory
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ISCA
2006
IEEE
187views Hardware» more  ISCA 2006»
13 years 11 months ago
A Case for MLP-Aware Cache Replacement
Performance loss due to long-latency memory accesses can be reduced by servicing multiple memory accesses concurrently. The notion of generating and servicing long-latency cache m...
Moinuddin K. Qureshi, Daniel N. Lynch, Onur Mutlu,...
ISCA
2005
IEEE
141views Hardware» more  ISCA 2005»
13 years 10 months ago
RegionScout: Exploiting Coarse Grain Sharing in Snoop-Based Coherence
It has been shown that many requests miss in all remote nodes in shared memory multiprocessors. We are motivated by the observation that this behavior extends to much coarser grai...
Andreas Moshovos
SIGCOMM
2004
ACM
13 years 10 months ago
Building a better NetFlow
Network operators need to determine the composition of the traffic mix on links when looking for dominant applications, users, or estimating traffic matrices. Cisco’s NetFlow ha...
Cristian Estan, Ken Keys, David Moore, George Varg...
SIGMETRICS
2006
ACM
174views Hardware» more  SIGMETRICS 2006»
13 years 11 months ago
Understanding the management of client perceived response time
Understanding and managing the response time of web services is of key importance as dependence on the World Wide Web continues to grow. We present Remote Latency-based Management...
David P. Olshefski, Jason Nieh
ECRTS
2006
IEEE
13 years 11 months ago
WCET-Centric Software-controlled Instruction Caches for Hard Real-Time Systems
Cache memories have been extensively used to bridge the gap between high speed processors and relatively slower main memories. However, they are sources of predictability problems...
Isabelle Puaut