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ICCD
2004
IEEE
103views Hardware» more  ICCD 2004»
14 years 1 months ago
A Fast Delay Analysis Algorithm for The Hybrid Structured Clock Network
This paper presents a novel approach to reducing the complexity of the transient linear circuit analysis for a hybrid structured clock network. Topology reduction is first used to...
Yi Zou, Yici Cai, Qiang Zhou, Xianlong Hong, Sheld...
ASPDAC
2005
ACM
131views Hardware» more  ASPDAC 2005»
13 years 6 months ago
Analysis of buffered hybrid structured clock networks
- This paper presents a novel approach for fast transient analysis of buffered hybrid structured clock networks. The new method applies structure reduction and relaxed hierarchical...
Yi Zou, Qiang Zhou, Yici Cai, Xianlong Hong, Sheld...
CDC
2009
IEEE
149views Control Systems» more  CDC 2009»
13 years 9 months ago
Robust stabilization of model-based uncertain singularly perturbed systems with networked time-delay
—In this paper, a robust stabilization of the uncertain singularly perturbed system via a networked state feedback with the transmission time-delay is addressed. Taking its nomin...
Zhiming Wang, Wei Liu, Haohui Dai, D. Subbaram Nai...
ICDCS
2005
IEEE
13 years 10 months ago
DISC: Dynamic Interleaved Segment Caching for Interactive Streaming
Streaming media objects have become widely used on the Internet, and the demand of interactive requests to these objects has increased dramatically. Typical interactive requests i...
Lei Guo, Songqing Chen, Zhen Xiao, Xiaodong Zhang
CODES
2005
IEEE
13 years 10 months ago
High-level synthesis for large bit-width multipliers on FPGAs: a case study
In this paper, we present the analysis, design and implementation of an estimator to realize large bit width unsigned integer multiplier units. Larger multiplier units are require...
Gang Quan, James P. Davis, Siddhaveerasharan Devar...