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» A Fast Routability-Driven Router for FPGAs
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FPGA
1998
ACM
176views FPGA» more  FPGA 1998»
13 years 8 months ago
A Fast Routability-Driven Router for FPGAs
Three factors are driving the demand for rapid FPGA compilation. First, as FPGAs have grown in logic capacity, the compile computation has grown more quickly than the compute powe...
Jordan S. Swartz, Vaughn Betz, Jonathan Rose
FPL
2005
Springer
136views Hardware» more  FPL 2005»
13 years 9 months ago
Architecture-Adaptive Routability-Driven Placement for FPGAs
Current FPGA placement algorithms estimate the routability of a placement using architecture-specific metrics. The shortcoming of using architecture-specific routability estimates ...
Akshay Sharma, Carl Ebeling, Scott Hauck
MAM
2006
95views more  MAM 2006»
13 years 4 months ago
Stochastic spatial routing for reconfigurable networks
FPGA placement and routing is time consuming, often serving as the major obstacle inhibiting a fast edit-compile-test loop in prototyping and development and the major obstacle pr...
André DeHon, Randy Huang, John Wawrzynek
FCCM
2005
IEEE
139views VLSI» more  FCCM 2005»
13 years 10 months ago
A Study of the Scalability of On-Chip Routing for Just-in-Time FPGA Compilation
Just-in-time (JIT) compilation has been used in many applications to enable standard software binaries to execute on different underlying processor architectures. We previously in...
Roman L. Lysecky, Frank Vahid, Sheldon X.-D. Tan
FPL
2006
Springer
96views Hardware» more  FPL 2006»
13 years 8 months ago
Reducing the Space Complexity of Pipelined Routing Using Modified Range Encoding
Interconnect delays are becoming an increasingly significant part of the critical path delay for circuits implemented in FPGAs. Pipelined interconnects have been proposed to addre...
Allan Carroll, Carl Ebeling