Abstract. There have been introduced a number of systems with evolvable hardware on a single chip. To overcome the lack of flexibility in these systems, we propose a single-chip e...
Online incremental evolution for a complex high-speed pattern recognition architecture has been implemented on a Xilinx Virtex-II Pro FPGA. The fitness evaluation module is entir...
In this paper, we propose an IPSec implementation on Xilinx Virtex-II Pro FPGA1 . We move the key management and negotiation into software function calls that run on the PowerPC p...
In this paper, we present profiling results of the Bluetooth standard implemented on the Xilinx Virtex II Pro device. The investigation is performed in two stages. First, we solel...
To increase the flexibility of single-chip evolvable hardware systems, we explore possibilities of systems with the evolutionary algorithm implemented in software on an onchip pr...
Kyrre Glette, Jim Torresen, Moritoshi Yasunaga, Yo...